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IBM zSeries 990
1
Technical Guide
1
May 2004
3
Second Edition (May 2004)
4
Contents
5
Contents v
7
Trademarks
10
Become a published author
12
Comments welcome
12
1.1 Introduction
15
1.2 z990 models
16
1.3.1 Processor
17
1.3.2 Memory
18
1.3.6 Spanned channels
19
1.3.7 I/O connectivity
20
Up to 1024 ESCON channels
21
FICON CTC function
22
FICON Cascaded Directors
22
OSA-Express
22
Gigabit Ethernet
23
1000BASE-T Ethernet
23
Token Ring
23
1.3.8 Cryptographic
24
Internal Coupling (IC)
26
1.3.11 Hardware consoles
27
1.3.12 Concurrent upgrades
27
Capacity BackUp (CBU)
28
1.3.13 Performance
29
1.3.15 Software
30
1.3.16 Software support
31
Software pricing
32
1.3.17 Summary
33
System structure and design
35
STI Slots
36
Memory cards
36
Memory Cards
37
Book 0Book 3 Book 1 Book 2
38
MRU 0 MRU 1
38
2.1.3 Memory
39
2.1.4 Ring topology
41
2.1.5 Connectivity
43
Book upgrade
44
Book front view
44
STI connectors
44
2.1.6 Frames and cages
45
I/O cages
46
2.1.7 The MCM
47
Figure 2-11 MCM chip layout
48
2.1.9 Summary
49
2.2 System design
50
2.2.2 Book design
51
Memory Card
52
MBA Card
52
2.2.3 Processor Unit design
53
Compression Unit on a chip
55
Without BHT:
56
With BHT:
56
IEEE Floating Point
57
Translation Lookaside Buffer
57
Instruction grouping
57
Extended Translation Facility
58
Central Processors
59
Internal Coupling Facilities
60
Purpose of a zAAP
61
System Assist Processors
62
Reserved processors
63
Application preservation
64
Sparing rules
64
2.2.5 Memory design
65
Memory allocation
66
Central storage (CS)
67
Expanded storage (ES)
67
2.2.6 Modes of operation
68
Logical Partitioning overview
69
Logically partitioned mode
72
* ’ and then
73
2.2.7 Model configurations
74
Software models
75
PU conversions
76
Capacity Backup (CBU)
77
Software model MSU values
78
2.2.8 Storage operations
79
ESA/390 mode
80
ESA/390 TPF mode
81
Coupling Facility mode
81
Linux Only mode
81
2.2.9 Reserved storage
82
2.2.12 I/O subsystem
83
2.2.13 Channel Subsystem
84
I/O system structure
85
3.1 Overview
86
Figure 3-2 z990 I/O cage
88
Domain I/O slots in domain
88
I/O Cage
90
CEC Cage
90
STI-2 Extender card
91
STI-3 Extender card
91
2084-B16 CEC Cage
92
I/O Cage 1 I/O Cage 2
92
2084-D32 CEC Cage
94
I/O Cage 1
95
/O Cage 2
95
3.3.1 I/O feature cards
96
PCIXCC 0868
97
PCICA 0862
97
I/O Cage 1 - Front
98
I/O cage slot
99
PCHID numbers
99
3.4 Connectivity
101
Configuration rules notes
102
Spanned and shared channels
103
3.4.2 ESCON channel
105
16-port ESCON channel sparing
107
Channel Sparing
108
3.4.3 FICON channel
109
FICON Express SX feature
110
3.4.4 OSA-Express adapter
111
HiperSockets function
116
ISC-3 link
117
ICB-4 link
118
ICB-3 link
118
ICB-2 link
118
IC links
119
3.4.7 Cryptographic features
120
Channel Subsystem
121
LCSS 0, 1, 2, 3 30 30 1024
122
Multiple Image Facility (MIF)
123
Logical partition number
123
Logical partition identifier
124
MIF Image ID (MIFID)
124
Logical partition name
124
4.1.3 Channel spanning
126
4.3 LCSS-related numbers
129
Cryptography
131
Chapter 5. Cryptography 121
133
Programming
134
Chapter 5. Cryptography 123
135
5.3.2 The PCICA feature
137
5.3.3 Configuration rules
138
Chapter 5. Cryptography 127
139
PCICA 6 2 12 16 30/30
139
PCIXCC 4 1 4 16 30/30
139
5.5 Software requirements
141
Software support
145
6.1 Operating system support
146
6.2 z/OS software support
146
G5, G6, z800, or z900
148
Planned z/OS V1.6 support
150
6.2.3 HCD support
152
6.2.4 Automation changes
152
6.2.5 SMF support
152
6.2.6 RMF support
153
6.2.7 ICKDSF requirements
153
6.2.8 ICSF support
153
Stand-alone dump
154
Automation
154
6.3 z/VM software support
157
6.5 TPF software support
158
6.6 Linux software support
159
6.8 Workload License Charges
162
Processor identification
163
Channel to channel links
164
Sysplex functions
167
7.1 Parallel Sysplex
168
High capacity
169
Dynamic workload balancing
169
Systems management
170
Resource sharing
170
Single system image
170
Message Time Ordering
171
External Reference ID
172
Link Type z990 Max
176
Peer mode links
177
Meaning of PARTITION
178
Function Setup
179
Function
180
7.3.1 Benefits
181
7.3.2 CF structure duplexing
182
7.3.3 Configuration planning
182
CF to CF link
183
CF structure duplexing
183
7.4.1 GDPS/PPRC
184
GDPS/PPRC HyperSwap™
185
Planned HyperSwap
186
Unplanned HyperSwap
186
GDPS FlashCopy® V2 support
187
7.4.2 GDPS/XRC
188
Application
189
IRD overview
190
7.5.1 LPAR CPU management
191
Value of CPU management
192
Workload type Priority
195
Unique LPAR cluster names
196
7.5.6 References
197
Capacity upgrades
199
8.1 Concurrent upgrades
200
Model upgrades
201
Planned upgrades
201
Unplanned upgrades
202
Capacity upgrade functions
202
CUoD for processors
203
CUoD for memory
205
+ Model upgrade
206
CUoD for I/O
207
Internet
210
Activation
213
Initiation
216
Ordering
216
$
217
8.5 Capacity BackUp (CBU)
218
CBU activation
220
Image upgrades
220
CBU deactivation
220
CBU testing
221
8.6 Nondisruptive upgrades
222
8.6.1 Upgrade scenarios
223
^ zSeries 990 Technical Guide
224
8.7.1 Balanced system design
231
Multi-book structure
232
Book 0 Book 1
233
8.7.2 Superscalar processors
234
8.8 Capacity measurements
235
LSPR workloads prior to z990
237
LSPR workloads for z990
238
CB-S 20% 10% 15% 17.5% 25%
240
20%----20%
240
20% 30% 20% 15% - 20%
240
Workload type
241
LSPR-Mix
241
(Default)
241
Environmental requirements
243
9.1 Introduction
244
9.2 Weights
245
9.3 Dimensions
246
Hardware Management Console
247
G5/G6 Series
249
different Hardware
250
Token-Ring LAN
251
Enterprise
252
Ethernet LAN
253
Token-Ring
255
Remote operations
256
Support Element
257
Fiber optic cabling services
261
Glossary 255
267
Glossary 257
269
ESCON channel
270
Glossary 259
271
Related publications
273
Online resources
274
Related publications 263
275
Numerics
277
(0.5” spine)
281
0.475”<->0.873”
281
250 <-> 459 pages
281
zSeries 990
284
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